//-------------------------------------------------------//
//-- bitclk:   位时钟 用来产生位输出时钟，1bit 1.25us
//-- frameclk: 帧时钟 用来同步帧输出，一帧由32bit + 200us
//--  FRAME_CYCLE:一帧总共占用的位数（有效位+复位时间）默认
//--              32bit+200us=192周期
//--  BIT_CNT    :一帧的有效位数，默认32周期
//-------------------------------------------------------//


module LightClk_Module
 #(
    parameter [9:0] FRAME_CYCLE = 10'd288,  
	 parameter [9:0] BIT_CNT     = 10'd128   
 )
 (
    input              clk ,
	 input              rstn,
	 output  reg        bitclk,
	 output  reg        frameclk
 );
 
   localparam [9:0]  FRAME_CYCLE_TH = FRAME_CYCLE-1;
	localparam [9:0]  BIT_CNT_TH     = BIT_CNT-1;
	
   reg [9:0]  framecnt = 10'd0;
	reg [3:0]  bitcnt   = 4'd0;
	//----------------------------------------------
	//--  描述：8M时钟需要10个周期产生1.25us计数
	//----------------------------------------------
   always@(posedge clk or negedge rstn)
   begin
	  if(rstn==1'b0)
	    bitcnt <= 4'd0;
	  else 
	    begin
		   bitcnt <= bitcnt + 1'b1;
			if(bitcnt>=4'd9)
			  bitcnt <= 4'd0;
	    end
   end
	
	//----------------------------------------------
	//--  描述：帧计数
	//----------------------------------------------
   always@(posedge clk or negedge rstn)
   begin
	  if(rstn==1'b0)
	    framecnt <= 10'd0;
	  else 
	    begin
		   if((framecnt < FRAME_CYCLE_TH)&&(bitcnt>=4'd9))
		     framecnt <= framecnt + 1'b1;
			else if((framecnt >= FRAME_CYCLE_TH)&&(bitcnt>=4'd9)) //1帧 840us
			  framecnt <= 10'd0;
	    end
   end
   
	//----------------------------------------------
	//--  描述：帧时钟产生
	//----------------------------------------------
	always@(posedge clk or negedge rstn)
   begin
	  if(rstn==1'b0)
	    frameclk <= 1'b0;
	  else
	    begin
			if((framecnt >= FRAME_CYCLE_TH)&&(bitcnt>=4'd9))        
			  frameclk <= 1'b1;
			else
			  frameclk <= 1'b0;
	    end
   end
	
	//----------------------------------------------
	//--  描述：位时钟产生
	//----------------------------------------------
	always@(posedge clk or negedge rstn)
   begin
	  if(rstn==1'b0)
	    bitclk <= 1'b0;
	  else
	    begin 
	      if((framecnt <= BIT_CNT_TH)&&(bitcnt==4'd0))
			  bitclk <= 1'b1;
	      else
			  bitclk <= 1'b0;
		 end
   end
endmodule